Recent technological advances in the semiconductor industry permitted dramatic increases in integrated circuit density and complexity. These improvements have led to a dramatic increase in their use in a variety of applications, especially digital applications. An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as static random access memory (SRAM) and dynamic random access memory (DRAM) circuits. The structure of such memory circuitry typically contains at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (which results in a low price), with DRAM cell size being typically between 6 F2 and 8 F2 (where F is the minimum feature size). However, with typical DRAM access times of approximately 50 nsec, DRAM is relatively slow compared to typical microprocessor speeds. SRAM is another common semiconductor memory that is much faster than DRAM. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density, with typical cell size being between about 60 F2 and 150 F2.
Recently, a new type of memory cells has been developed. These cells consist of a control port that is capacitively coupled to a relatively thin thyristor body. The thyristor body is sufficiently thin to permit modulation of the potential of the thyristor body in response to selected signals capacitively coupled via the control port. Such capacitively-coupled signals are used to enhance switching of the thyristor-based device between current-blocking and current-conducting states. One advantage of this type of cells is that the cell size is much smaller than the SRAM cells. Further, the access time of this type of cells is much faster than DRAM. Details of such thinly capactively coupled thyristor memory cells can be found in U.S. Pat. No. 6,229,161.
In many digital applications, a reduction in memory write time generally leads to improved performance. Consequently, it is desirable to reduce memory write time of such thyristor-based devices.